1. Field of the Invention
The present invention relates to a device for deinterleaving interleaved digital transmission data, and more particularly, to a deinterleaving device which releases a plurality of types of interleaving simultaneously.
2. Description of the Related Art
In recent years, digitalization in broadcasting technology has been in rapid progress. For example, terrestrial digital audio broadcasting employing a transmission method called orthogonal frequency division multiplex (OFDM) has been realized. In such a broadcasting method, in general, (1) an audio signal is coded after an error correction code is added thereto, (2) the coded data is divided into blocks (normally called xe2x80x9cframesxe2x80x9d) of a predetermined length, and (3) each frame is constructed of a plurality of OFDM symbols. In addition to the above, processing steps of (4) rearranging data between frames (time interleave) and (5) changing the order of sub-carriers in a symbol (frequency interleave) may be performed. By combining the two types of interleave (4) and (5) with error correction, the audio signal can be substantially restored to its original state even if continuous data on a time axis and a frequency axis are partially missing.
If such radio wave is reflected from a tall building, a mountain, and the like during reception of broadcasting, the frequency characteristic of a transmission path is no longer flat, causing a degradation of a received signal, called multi-path interference, in some cases. In such cases, the receiving power of continuous sub-carriers on a frequency axis drops simultaneously (frequency selective phasing). Therefore, if frequency interleaving is not performed, data error tends to occur in bursts, and thus the effect of an error correction code is unlikely to be obtained. Also, in the case of reception of broadcasting in a moving car and the like, impulse-like noise from an ignition plug of an engine and the like and instantaneous reduction of the electric field intensity may possibly occur. In order to avoid influences from such occurrences, interleave on a time axis is also required.
For the above reasons, time and frequency interleaves are indispensable for digital broadcasting employing the OFDM method. Receivers of such broadcasting are therefore required to include a function of deinterleaving. For example, Japanese Laid-Open Publication No. 8-316933 and Japanese National Phase PCT Laid-Open Publication No. 9-509818 and No. 9-509819 disclose a same construction of a receiver for digital audio broadcasting (hereinbelow, abbreviated as DAB) which has a function of releasing time and frequency interleaves.
In Japanese National Phase PCT Laid-Open Publication No. 9-509819 (see FIG. 2 of this publication), for example, frequency interleave is released when an output of a demodulator DEM is written in a demodulator output buffer DOB. The resultant data is temporarily written in a first section of a time deinterleave memory TDM(1). The frequency-deinterleaved data is then returned to the demodulator output buffer DOB and written this time in a second section of the time deinterleave memory TDM(2). During this writing of data in TDM(2), time interleave is released. The resultant data released from both time and frequency interleaves is then transferred to a deinterleaver output buffer (IOB) and then input to a Viterbi decoder DEC for error correction.
In general, delay occurs when serial data is interleaved. In order to deinterleave, it is necessary to provide a memory device for temporarily storing standby data during the delay time. Such a memory device is generally a semiconductor memory such as a DRAM, an SRAM, and a register. In the above exemplified receiver for DAB, the demodulator output buffer DOB for releasing frequency interleave and the first section of the time deinterleave memory TDM(1) for releasing time interleave correspond to the memory device for temporarily storing data described above. The interleave-specific delay of time interleave is enormously larger than that of frequency interleave. Accordingly, while the memory capacity of DOB is 12 kbits, that of TDM is as large as 1,024 kbits (1 kbit=1,024 bits). In this case, it should be noted that the memory capacity of the time deinterleave memory TDM is limited on the assumption that only part of a plurality of multiplexed services in a DAB signal is demodulated.
If the output data rate (output speed) after deinterleaving is not matched with the input data rate of an error corrector, a storage device called a buffer (normally, a memory) is required to achieve matching of these rates. Some error correctors read data intermittently depending on the error correction coding method. In general, therefore, the above two data rates are not matched with each other. In the above exemplified receiver for DAB, the second section of the time deinterleave memory TDM(2) and the deinterleaver output buffer IOB serve to match the data rates.
The above conventional device requires high-speed and complicated processing, which is not easily realized by a general purpose processor. Such processing is normally performed by an exclusive signal processing LSI (large scale integrated circuit). As of today, however, it is not preferable economically to mount a large-capacity memory such as the time deinterleave memory in a signal processing LSI. Therefore, the conventional deinterleaving device as described above has a construction that a general external large-capacity memory is added to an exclusive signal processing LSI.
The above conventional receiver for DAB has the following problems. Since frequency and time interleaves are separately released, respective memories for releasing these interleaves are required. If a memory for frequency interleave and an output buffer are incorporated in a signal processing LSI, production cost of the LSI increases since memories normally occupy a large area on a chip. In the case where such memory and buffer are not incorporated in the LSI, external memories are separately required, resulting in increasing the cost of the receiver.
In reality, it is possible to release both time and frequency interleaves using a single external memory. For example, data may be written in a memory so that the data is arranged in a state that frequency interleave has been released, and time interleave may be released when the data is read. In this construction, however, access to random addresses is performed in the memory during both write and read operations. In such random access, if the input/output data rates are high, a DRAM having long random read/random write times fails to catch up with the processing speed.
Hereinbelow, the processing speed will be described, taking as an example a receiver of a DAB signal used in broadcasting in Europe. In European DAB standards, the coding rate to an original code is 1/4 at minimum. In order to obtain an output data rate of 1.536 Mbps after error correction, an output data rate of four times the above data rate, i.e., 4.096 MHz, is required after deinterleaving. The input data rate is 4.096 MHz, and the average of the input/output data rates is 5.12 MHz.
The random read or random write cycle time is 110 ns for a standard DRAM having an access time of 60 ns. Therefore, since 220 ns is required for one random read/random write, it is not possible to obtain an average input/output data rate equal to or more than 4.545 MHz (=1/220 ns). In order to obtain the output data rate of 6.144 MHz, it is necessary to temporarily store data in a buffer (i.e., a large-capacity memory) before being output or to use an SRAM and the like capable of realizing high-speed random access, in place of the DRAM. However, using a buffer increases production cost of the LSI, and an SRAM has a high cost per bit compared with a DRAM.
The deinterleaving device of this invention deinterleaves an input transmission frame and outputs the deinterleaved frame, the transmission frame being obtained by performing inter-frame interleaving for an original frame to form an intermediate frame and performing inner-segment interleaving for at least one data segment included in the intermediate frame. The deinterleaving device includes: a memory; a data write section for receiving the transmission frame and writing the transmission frame into the memory; and a data read section for releasing the inter-frame interleaving and the inner-segment interleaving simultaneously when reading data from the memory and outputting the data.
In one embodiment of the invention, the data write section receives data in a plurality of transmission frames and writes the data into the memory, and the data read section determines the order of the data in each of the transmission frames in a state where the inter-frame interleaving and the inner-segment interleaving are released by calculating backward a rearranging rule of the inner-segment interleaving and a rearranging rule of the inter-frame interleaving, reads the data from the memory in the determined order, and outputs the data.
In another embodiment of the invention, the data write section includes: a data counter for counting the number of data in a transmission frame; a frame counter for counting the number of transmission frames; a first frame head address generator for generating an address in the memory at which head data of the transmission frame is to be stored based on a value of the frame counter; and a first adder for summing a value of the data counter and an output value of the first frame head address generator and outputting the result as an address in the memory.
In still another embodiment of the invention, the data read section includes: a counter for counting the number of data read requests; a second frame head address generator for generating an address in the memory at which the head data of the transmission frame is stored based on a value of the counter and a value of the frame counter of the data write section; a ROM for storing a rearranging rule of the inner-segment interleaving; a first operator for calculating a data segment to which desired output data belongs; a second operator for calculating a relative position of the desired output data in the data segment using the ROM; and a second adder for summing output values of the second frame head address generator, the first operator, and the second operator and outputting the result as an address in the memory.
In still another embodiment of the invention, the transmission frame includes, at a stage of the intermediate frame, a data segment for which the inter-frame interleaving has been performed and a data segment for which the inter-frame interleaving has not been performed, the data write section writes the data segment for which the inter-frame interleaving has been performed and the data segment for which the inter-frame interleaving has not been performed at different storage positions of the memory, and the data read section releases the inter-frame interleaving and the inner-segment interleaving simultaneously for the data segment for which the inter-frame interleaving has been performed when reading data from the memory and outputs the data, while the data read section releases the inner-segment interleaving for the data segment for which the inter-frame interleaving has not been performed when reading data from the memory and outputs the data.
In still another embodiment of the invention, the data segments are transmitted via sub-carriers included in at least one symbol constituting orthogonal frequency division multiplex, and the transmission frame includes a plurality of symbols constituting orthogonal frequency division multiplex.
In still another embodiment of the invention, the memory is a DRAM having a fast page mode, and the data write section writes at least two consecutive data in the transmission frame into continuous addresses in the DRAM in the fast page mode.
In still another embodiment of the invention, the data segment is transmitted via sub-carriers included in at least one symbol constituting orthogonal frequency division multiplex, a guard interval is added to the symbol constituting orthogonal frequency division multiplex, the transmission frame includes a plurality of symbols constituting orthogonal frequency division multiplex, an orthogonal frequency division multiplex demodulator is connected upstream of the deinterleaving device, and refresh operation of the DRAM is performed during the guard interval.
Alternatively, the deinterleaving device of this invention deinterleaves an input transmission frame and outputs the deinterleaved frame, the transmission frame being obtained by performing inter-frame interleaving for an original frame to form an intermediate frame and performing inner-segment interleaving for at least one data segment included in the intermediate frame. The deinterleaving device includes: a memory; a data write section for releasing the inter-frame interleaving and the inner-segment interleaving simultaneously when writing data in the memory; and a data read section for reading data from the memory and outputting the data.
In one embodiment of the invention, the data write section receives data in a plurality of transmission frames, determines the order of the data in each of the transmission frames in a state where the inter-frame interleaving and the inner-segment interleaving are released by calculating backward a rearranging rule of the inner-segment interleaving and a rearranging rule of the inter-frame interleaving, and writes the data in the memory in the determined order.
In another embodiment of the invention, the data segments are transmitted via sub-carriers included in at least one symbol constituting orthogonal frequency division multiplex, and the transmission frame includes a plurality of symbols constituting orthogonal frequency division multiplex.
In still another embodiment of the invention, the memory is a DRAM having a fast page mode, and the data write section writes at least two consecutive data in the transmission frame at continuous addresses in the DRAM in the fast page mode.
In still another embodiment of the invention, the data segment is transmitted via sub-carriers included in at least one symbol constituting orthogonal frequency division multiplex, a guard interval is added to the symbol constituting orthogonal frequency division multiplex, the transmission frame includes a plurality of symbols constituting orthogonal frequency division multiplex, an orthogonal frequency division multiplex demodulator is connected upstream of the deinterleaving device, and refresh operation of the DRAM is performed during the guard interval.
Alternatively, the deinterleaving device of this invention deinterleaves an input transmission frame and outputs the deinterleaved frame, the transmission frame being obtained by performing inter-frame interleaving for an original frame including at least one channel to form an intermediate frame multiplexed by allocating the channel at a predetermined channel start position and performing inner-segment interleaving for at least one data segment included in the intermediate frame. The deinterleaving device includes: a memory; a data write section for writing the transmission frame into the memory; and a data read section for releasing the inter-frame interleaving and the inner-segment interleaving for data in the channel simultaneously by referring to the channel start position of the channel when the channel start position is designated during reading of data from the memory, and outputting the data of the channel.
In one embodiment of the invention, the data write section receives data in a plurality of transmission frames and stores the data in the memory, and the data read section determines the order of the data in each of the transmission frames in a state where the inter-frame interleaving and the inner-segment interleaving are released by calculating backward a rearranging rule of the inner-segment interleaving and a rearranging rule of the inter-frame interleaving, reads the data in the memory in the determined order, and outputs the data.
In another embodiment of the invention, the data read section calculates a storage position of data in the memory based on the channel start position and the number of data read requests when the channel start position is designated during reading of data from the memory.
In still another embodiment of the invention, the data read section includes: a register for storing the channel start position; a counter for counting the number of data read requests; and an operator for calculating the storage position of data in the memory based on values of the register and the counter.
In still another embodiment of the invention, during reading of data from the memory, when the data read section receives a channel multiplexing construction change signal indicating a change of a channel multiplexing construction of the original frame, the data read section releases the inter-frame interleaving and the inner-segment interleaving for data in the channel simultaneously by referring to an old channel start position before the receipt of the channel multiplexing construction change signal and a new channel start position after the receipt of the channel multiplexing construction change signal, and outputs the data of the channel.
In still another embodiment of the invention, when the data read section receives the channel multiplexing construction change signal, the data read section selects one of the old channel start position and the new channel start position based on the old and new channel start positions, the number of data read requests, and the number of transmission frames, and calculates the storage position of the data in the memory.
In still another embodiment of the invention, the data read section includes: a register for storing the old and new channel start positions and renewing the old and new channel start positions in response to the channel multiplexing construction change signal; a first counter for counting the number of data read requests; a second counter for counting the number of transmission frames, the second counter being initialized on receipt of the channel multiplexing construction change signal; and an operator for calculating a storage position of data in the memory based on values of the register, the first counter, and the second counter.
In still another embodiment of the invention, the transmission frame includes, at a stage of the intermediate frame, a data segment for which the inter-frame interleaving has been performed and a data segment for which the inter-frame interleaving has not been performed, the data write section writes the data segment for which the inter-frame interleaving has been performed and the data segment for which the inter-frame interleaving has not been performed into different storage positions of the memory, and the data read section releases the inter-frame interleaving and the inner-segment interleaving simultaneously for the data segment for which the inter-frame interleaving has been performed when reading data from the memory and outputs the data, while the data read section releases the inner-segment interleaving for the data segment for which the inter-frame interleaving has not been performed when reading data from the memory and outputs the data.
In still another embodiment of the invention, the data segments are transmitted via sub-carriers included in at least one symbol constituting orthogonal frequency division multiplex, and the transmission frame includes a plurality of symbols constituting orthogonal frequency division multiplex.
In still another embodiment of the invention, the memory is a DRAM having a fast page mode, and the data write section writes at least two consecutive data in the transmission frame at continuous addresses in the DRAM in the fast page mode.
In still another embodiment of the invention, the data segment is transmitted via sub-carriers included in at least one symbol constituting orthogonal frequency division multiplex, a guard interval is added to the symbol constituting orthogonal frequency division multiplex, the transmission frame includes a plurality of symbols constituting orthogonal frequency division multiplex, an orthogonal frequency division multiplex demodulator is connected upstream of the deinterleaving device, and refresh operation of the DRAM is performed during the guard interval.
Thus, the invention described herein makes possible the advantages of (1) providing a less expensive deinterleaving device which does not require a frequency interleave memory nor an output buffer, and (2) providing a deinterleaving device capable of realizing a high output data rate using an inexpensive DRAM as an external memory.